This invention relates to a flip-flop for use in applications in which the flip-flop may be optionally bypassed—e.g., as an output latch for programmable logic circuitry whose output may be registered or unregistered. More particularly, this invention relates to such a flip-flop having a low-power mode for use when bypassed.
A flip-flop circuit is a well known and simple circuit for holding the value of an input for at least one clock cycle in a clocked system. For this reason, flip-flops frequently are used as output latches or registers in programmable logic devices. In such an application, the output of a programmable logic element typically is routed to the flip-flop, where it may be made available at the next clock edge, for one full clock cycle, for use by additional logic or as an output of the programmable logic device. It is also typical to provide a bypass route for the output of the programmable logic element, allowing it to be routed asynchronously to additional logic or to a device output.
A common configuration for an output bypass as just described is to route the programmable logic element output both to the input of the flip-flop and to an input of an output multiplexer. The output of the flip-flop also is routed to an input of the output multiplexer, and the multiplexer can be controlled to select either the direct, unregistered logic output or the registered output of the flip-flop. When this configuration is used, the flip-flop, which also is connected to the system clock, continues to switch at every clock cycle, even when the output multiplexer selects the unregistered bypass output. In addition, if the input data vary, that may also cause switching of components within the flip-flop. As a result, the flip-flop consumes power even though it is not being used.
In view of the foregoing it would be desirable to be able to provide a latch circuit that consumes less power in the bypass mode than it does in the latched mode.